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Tunneling Amplifier

Published: at 12:39 AM (3 min read)

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Description

The tunneling current in a scanning tunneling microscope (STM) arises from the quantum mechanical tunneling of electrons between a conductive sample and a sharp metallic tip under an applied bias voltage. This current is typically in the picoampere (pA) to nanoampere (nA) range, often below the detection threshold of standard analog-to-digital converters (ADCs). Accurate measurement of this current necessitates a high-impedance, low-noise preamplifier with ultra-high gain and minimal input bias current. We therefore implemented a transimpedance amplifier (TIA) using the OPA928DT from Texas Instruments, optimized for ultra-low input bias current and low voltage noise density.

tunneling amplifier schmematic

Amplifier Operation

The transimpedance amplifier converts an input current ItipI_{\text{tip}} into a voltage VoutV_{\text{out}} via a feedback resistor RfR_f, according to the ideal equation:

Vout=ItipRf.V_{\text{out}} = -I_{\text{tip}} \cdot R_f.

In our design, Rf=100MΩR_f = 100\mathrm{M\Omega}, resulting in a voltage gain sufficient to resolve currents as small as 10pA. The tip is connected to the inverting input of the op-amp, while the non-inverting input is held at analog ground (0V). The op-amp output feeds back through the large RfR_f, and an additional small series resistor (220Ω\Omega) at the output node helps isolate the amplifier from capacitive loading due to long cables, improving phase margin and overall stability.

Noise Considerations

The total noise in a transimpedance amplifier includes contributions from:

Given the very large RfR_f, thermal noise is significant and sets a practical limit on sensitivity. The OPA928, however, offers extremely low ini_n and ene_n, and its unity-gain bandwidth of 10~MHz ensures sufficient open-loop gain for our application.

Power Rails and Decoupling

Power to the amplifier is supplied through a two-pin header (J1) that delivers regulated ±15\pm15V analog rails. Each rail is decoupled locally with a 4.7μ\muF electrolytic capacitor in parallel with a 100~nF ceramic capacitor. This local bypass network helps reduce high-frequency power supply noise and prevents oscillations by stabilizing the op-amp power inputs.

Guarding and Layout Strats

Due to the extremely high input impedance and sub-nanoampere current levels, special layout techniques are essential to prevent signal corruption due to leakage currents. We employed a comprehensive guarding strategy:

guard pour

Output and Interface

The amplifier’s output, labeled Preamp OUT, is routed to a test pad (TP1) and a shielded connector for delivery to the ADC on the STM mainboard. This output signal, a voltage proportional to tunneling current, is digitized and used in both imaging and feedback control. The output stage of the amplifier is configured to drive a capacitive load and is verified to remain stable under expected cable parasitics.

layout